1. Field
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In an LSI of a so-called 90 nm node, or finer in recent years, further microminiaturization has been required. As a result, it becomes difficult to improve the performance of a transistor. This is because since a standby off-leak current is increased according to the reduction in the gate length of transistor, when the off-leak current is intended to be suppressed to a fixed level, it is extremely difficult to improve the current drive capability of the transistor. Therefore, a new approach for improving the capability of the transistor has been investigated.
There is a strained silicon technique as one attempt of the approach. The strained silicon technique is a technique which improves the current drive capability by improving the carrier mobility in such a manner that the band structure is changed by applying a stress to a channel region so as to reduce the effective mass of the carriers.
It is known that in a p-channel MOS transistor, the carrier mobility is improved by applying a uniaxial compressive stress to a channel region. As a specific example in which a compressive stress is applied to the channel region, there is proposed a transistor having a so-called embedded structure in which a recessed portion is formed in a source/drain region and in which a SiGe layer is embedded into the recessed portion by an epitaxial method (Japanese Patent Laid-Open No. 2006-186240).
On the other hand, in an n-channel MOS transistor, there is proposed a transistor having a so-called embedded structure in which a recessed portion is formed in a source/drain region similarly to the p-channel MOS transistor and in which a SiC layer is embedded into the recessed portion by an epitaxial method.
Since SiGe has a lattice constant larger than that of silicon, a crystal of a SiGe layer is, in a sense, forcibly lattice-matched with a silicon substrate in the substrate in-plane direction. Thereby, the silicon substrate is expanded in the direction perpendicular to the substrate. As a result, a compressive strain is introduced into the channel region in the substrate in-plane direction, that is, in the channel direction, so that a compressive stress is applied to the channel region. The symmetry of the Si crystal which forms the channel region is locally changed as a result of the uniaxial compressive stress being applied to the channel region. Further, according to the change in symmetry, the degeneration between the heavy hole valence band and the light hole valence band is eliminated, so that the hole mobility in the channel region is increased to thereby improve the operating speed of the transistor. The increase in the hole mobility effected by the stress locally induced in the channel region, and the improvement in the transistor operating speed resulting from the increase in the hole mobility, remarkably appear in an ultrafine semiconductor device having a gate length of 100 nm or less, in particular.
On the other hand, in the case of a SiC layer, since SiC has a lattice constant smaller than that of silicon, the crystal of the SiC layer is forcibly lattice-matched with the silicon substrate in the substrate in-plane direction. As a result, a tensile strain is introduced into the channel region in the substrate in-plane direction, that is, in the channel direction, so that a tensile stress is applied to the channel region.